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PCA24S08 1024 x 8-bit CMOS EEPROM with access protection
Product data 2004 May 10
Philips Semiconductors
Philips Semiconductors
Product data
1024 x 8-bit CMOS EEPROM with access protection
PCA24S08
DESCRIPTION
The PCA24S08 provides 8192 bits of serial electrically erasable and programmable Read-only memory (EEPROM) organized as 1024 words of 8 bits each. Data bytes are received and transmitted via the serial I2C-bus. Access permissions limiting reads or writes are set via the I2C-bus to isolate blocks of memory from improper access. The PCA24S08 is intended to be pin compatible with standard 24C08 serial EEPROM devices except for pins 1, 2, and 3, which are address pins in the standard part. Other exceptions to the PCA24C08 serial EEPROM datasheet are noted the "Serial EEPROM Exception" section later in this document. All bits are sent to or read from the device, most significant bit first, in a manner consistent with the 24C08 serial EEPROM. The bit fields in this document are correspondingly listed with the MSB on the left and the LSB on the right. The EEPROM memory is broken up into 8 blocks of 1 k bits (128 bytes) each. Within each block, the memory is physically organized in to 8 pages of 128 bits (16 bytes) each. In addition to these 8 k bits, there are two more 128-bit pages that are used to store the access protection and ID information. There are a total of 8448 bits of EEPROM memory available in the PCA24S08. Access protection (both read and write) is organized on a block basis for blocks 1 through 7 and on a page and a block basis for block 0. Protection information for these blocks and pages is stored in one of the additional pages of EEPROM memory that is addressed separately from the main data storage array. See "Access Protection" for more details. The ID value (see "ID Configuration") is located in the ID page of the EEPROM, the second of the additional 16 byte pages. Writes from the serial interface may include from one to 16 bytes at a time, depending on the protocol followed by the bus master. All page accesses must be properly aligned to the internal EEPROM page. The EEPROM memory offers an endurance of 100,000 write cycles per byte, with 10 year data retention. Writes to the EEPROM take less than 5 ms to complete. After manufacturing, all EEPROM bits will be set to a value of `1'.
FEATURES * Non-volatile storage of 8 kbits organized as 8 blocks of 128 bytes
each
* * * * * * * * * * * * * * * *
I2C interface logic Compatible with 24C08 Serial EEPROM, and alternate source of Atmel AT24RF08C without the RF interface Write operation: - Byte write mode - 16-byte page write mode Read operation: - Sequential read - Random read Programmable access protection to limit reads and writes Lock/unlock function Write protect feature protecting the full memory array against write operations Self timed write cycle Internal power-on reset High reliability: - Ten years non-volatile data retention time - 100,000 write cycle endurance Low power CMOS technology Operating power supply voltage range of 2.5 V to 3.6 V 0 to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO8, TSSOP8
ORDERING INFORMATION
PACKAGES 8-pin plastic SO 8-pin plastic TSSOP TEMPERATURE RANGE -40 C to +85 C -40 C to +85 C ORDER CODE PCA24S08D PCA24S08DP TOPSIDE MARK P24S08 PS08 DRAWING NUMBER SOT96-1 SOT505-1
Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
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Philips Semiconductors
Product data
1024 x 8-bit CMOS EEPROM with access protection
PCA24S08
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER SYMBOL n.c. PROT GND SDA SCL WP VDD NAME AND FUNCTION not connected Active-LOW protect reset input Ground Serial data open drain I/O Serial clock open drain input Active-HIGH write protect input Supply voltage 1, 2 3 4 5 6
SW02220
n.c. 1 n.c. PROT GND 2 3 4
8 7 6 5
VDD WP SCL SDA
7 Figure 1. 8 pin configuration 8
BLOCK DIAGRAM
PCA24S08
SDA SCL INPUT FILTER WP PROT
I2C BUS CONTROL LOGIC
BYTE COUNTER
EEPROM 8 PAGES (8 x 128 bytes each) ACCESS PROTECTION
SEQUENCER
DIVIDER (/ 128)
BYTE LATCH (8 BYTES)
ADDRESS POINTER
IDENTIFICATION NUMBER
EE CONTROL
VDD
POWER-ON RESET
TIMER (/ 16)
OSCILLATOR
GND
SW02140
Figure 2. Block diagram
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Philips Semiconductors
Product data
1024 x 8-bit CMOS EEPROM with access protection
PCA24S08
DEVICE ADDRESSING
Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA24S08 is shown in Figure 3.
1 0 1 0 1 B2 B1 R/W
WRITE OPERATIONS
Write operations on the device can be performed only when WP is held LOW. When WP pin is held HIGH, content of the full memory is protected (Block 0 to Block 7, APP Registers, ID Page), and no write operation is allowed. Byte/word write: Write command may be used to set the address for a subsequent Read command. For a write operation, the PCA24S08 requires a second address field. The address field associated with the two software selectable bits in the slave address is a word address providing access to the 1024 bytes of memory, as shown in Figure 4. Upon receipt of the word address, the PCA24S08 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. Word address is automatically incremented. Figure 5 shows how the memory array is addressed when the slave address byte and address field byte are sent. The master terminates the transfer by generating a STOP condition. After this STOP condition, the Erase/Write (E/W) cycle starts and the I2C-bus is free for another transmission. Up to 16 bytes of data can be written in the slave writing sequence (E/W cycle).
FIXED
SOFTWARE SELECTABLE
SW02221
Figure 3. Slave address The last bit of the slave address defines the operation to be performed. When set to logic 1, a read operation is selected, while logic 0 selects a write operation. Bits B2 and B1 in the slave address represent the 2 most significant bits of the word to be addressed. The third device address bit in the I2C protocol that is usually matched to A2 (pin 3) on a standard 24C08 serial EEPROM is internally connected HIGH, so device addresses A8h through AFh (hex) are used to access the memory on the chip.
BYTE 0 0 PAGE 0 0 BLOCK 0 0 0 0 0 0 0 BYTE 15 1 1 1 1 0 0 0
BYTE 0 PAGE 7 1 1 1 BYTE 15 1 1 1 1 0 0 0
BYTE 0 0 PAGE 0 0 BLOCK 7 BYTE 0 1 1 1 0 PAGE 7 1 1 1 BYTE 15 1 1 1 1 0 0 0 0 0 1 BYTE 15 1 1 1 0 0 0
1
0
1
0
1
B2
B1 R/W
B0 P2
P1
P0
A3
A2
A1 A0
FIXED BLOCK NUMBER
PAGE NUMBER
BYTE ADDRESS
SW02222
Figure 4. Memory addressing 2004 May 10 4
Philips Semiconductors
Product data
1024 x 8-bit CMOS EEPROM with access protection
PCA24S08
The general command encoding used by the serial port for EEPROM accesses is shown below in Device Access Examples, where B2-0 is the block number, P2-0 is the page number within the block and A3-0 is the byte address within the page. Bits denoted as "x" are ignored by the device.
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
S
1
0
1
0
1
B2 B1
0
A
B0 P2 P1 P0
A3
A2 A1 A0
A
DATA
A
DATA
A
P
R/W WORD ADDRESS
WORD ADDRESS AUTO INCREMENT WORD ADDRESS AUTO INCREMENT WORD ADDRESS
SW02103
Figure 5. Auto-increment memory word address; two byte write
Page write: The PCA24S08 is capable of a 16-byte page write operation. It is initiated in the same manner as the byte write operation. The master can transit 16 data bytes within one transmission. After receipt of each byte, the PCA24S08 will respond with an acknowledge. The typical E/W time in this mode is 5 ms. After the receipt of each data byte, the four low-order bits of the word address are internally incremented. The six high-order bits of the address remain unchanged. The slave acknowledges the reception of each data byte with an ACK. The I2C-bus data transfer is terminated by the master after the 16th byte of data with a STOP condition. After a write to the last byte in a page, the internal
address is wrapped around to point to the beginning of that page. If the master transmits more than 16 bytes prior to generating the STOP condition, no acknowledge will be given on the 17th (and following) data bytes and the whole transmission will be ignored and no programming will be done. As in the byte write operation, all inputs are disabled until completion of the internal write cycles. After this STOP condition, the E/W cycle starts and the I2C-bus is free for another transmission. During the E/W cycle the slave receiver does not acknowledge if addressed via the I2C-bus.
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
S
1
0
1
0
1
B2 B1 WORD ADDRESS
0 R/W
A
B0 P2 P1 P0
A3
A2 A1 A0
A
DATA
A
DATA + 1
A
P
WORD ADDRESS AUTO INCREMENT WORD ADDRESS AUTO INCREMENT WORD ADDRESS ACKNOWLEDGE FROM SLAVE
DATA + 15
A
A
LAST BYTE AUTO INCREMENT WORD ADDRESS
SW02104
Figure 6. Page write operation: 16 bytes
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Philips Semiconductors
Product data
1024 x 8-bit CMOS EEPROM with access protection
PCA24S08
READ OPERATIONS
Read operations are initiated in the same manner as write operations with the exception that the LSB of the slave address is set to logic 1. The lower 7 bits of the word address are incremented after each transmission of a data byte during a read. The three MSBs of the word address are not changed when the word counter overflows. Thus, the word address overflows from 127 to 0, and from 255 to 128. After the read of the last byte within a block, the internal serial address wraps around to point at the beginning of that block.
ACKNOWLEDGE FROM SLAVE S 1 0 1 0 1 B2 B1 0 A B0 P2 P1 P0 A3 A2
ACKNOWLEDGE FROM SLAVE A1 A0 A S 1 0 1 0 1 X
ACKNOWLEDGE FROM MASTER X 1 R/W A DATA
ACKNOWLEDGE FROM MASTER A
R/W WORD ADDRESS FIRST PART
WORD ADDRESS SECOND PART
AT THIS MOMENT MASTER TRANSMITTER BECOMES MASTER RECEIVER AND EEPROM SLAVE TRANSMITTER
n BYTES AUTO INCREMENT WORD ADDRESS NO ACKNOWLEDGE FROM MASTER DATA A P
LAST BYTE AUTO INCREMENT WORD ADDRESS
SW02223
Figure 7. Master reads PCA24S08 slave after setting word address (write word address: read data); sequential read
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM MASTER
NO ACKNOWLEDGE FROM MASTER
S
1
0
1
0
1
X
X
1 R/W
A
DATA n BYTES
A
DATA
A
P
LAST BYTES AUTO INCREMENT WORD ADDRESS AUTO INCREMENT WORD ADDRESS
SW02224
Figure 8. Master read PCA24S08 immediately after first byte (read mode); current address read
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Philips Semiconductors
Product data
1024 x 8-bit CMOS EEPROM with access protection
PCA24S08
ACCESS PROTECTION
Write operation on the Access protection registers can be performed when WP pin LOW. If the WP pin is HIGH all write operations are prohibited from the serial port, although write commands may be used to set the address for a subsequent read command. All access protection bits are stored on a separate page of the EEPROM that is not accesses using the normal commands of a PCA24C08 memory. See the "Access Protection Page" section for more detail on this information.
will happen in the byte value. The device does not go to an E/W cycle and can be accessed immediately. If a block is protected and only read operation is allowed (the corresponding APP register has its PB bits programmed to 10), a write operation to this block is not acknowledged (Slave Address and Register pointer only are acknowledged). The device does not go to an E/W cycle and can be accessed immediately. S - Addr+W - ACK - Reg Pointer - ACK - Data - NACK This applies to: - EEPROM Block 0 to Block 7, controlled by PB0 to PB7 - The last 7 bytes of the APP block (09H to 0FH) and the ID page (10H to 1FH) controlled by PBAP If a block is protected and neither read operation nor write operation is allowed (the corresponding APP register has its PB bits programmed to 00 or 01), a write operation to this block is not acknowledged (Slave Address and Register pointer only are acknowledged). S - Addr+W - ACK - Reg Pointer - ACK - Data - NACK A read operation to this block is not allowed. S - Addr+W - ACK - Reg Pointer - ACK - Sr - Addr+R - NACK
RFID ACCESS FIELDS (RF)
Even though the PCA24S08 does not have the RFID capability, RFID access fields (RF) can be stored in order to keep existing software compatibility. The fields are stored in the EEPROM and organized as follows: MSB 0 0 1 1 LSB 0 1 0 1 FUNCTION No accesses permitted from RFID port No accesses permitted from RFID port Read only from RFID port No restrictions for RFID accesses
PROTECTION BITS (PB)
The protection bits fields in the Access Protection Page determine what type of accesses will be permitted via the serial port for each of the blocks on the chip. If an illegal access is attempted, the command will be NACK'ed. The MSB, if clear, prohibits all access to the block, and the LSB if clear prohibits writes. The fields are stored in the EEPROM and are organized as follows: MSB 0 0 1 1 LSB 0 1 0 1 FUNCTION No accesses permitted in the block No accesses permitted in the block Read only, writes cause a NACK Read/write --No access constraints for data within this block
S - Addr+W - ACK - Reg Pointer - ACK - P - S - Addr+R - NACK This applies to: - EEPROM Block 0 to Block 7, controlled by PB0 to PB7 - The last 7 bytes of the APP block (09H to 0FH) and the ID page (10H to 1FH) controlled by PBAP
BLOCK 0 WRITE PROTECTION BITS
The PCA24S08 provides a mechanism to divide block 0 into eight 128-bit (16 byte) pages that can be individually protected against writes. These eight write protection (WPN) bits are stored within a byte of the access protection page and are organized such that the LSB protects the first 128 bits and so on. If a bit in this byte is set to a one and the PB0 field is set to 11, then writes are permitted on the page corresponding to the WPN bit. If the WPN bit is set to a 0 or the PB0 is any value other than 11, then writes are not permitted in that page. The Write Protection hierarchy for serial accesses is shown in Figure 6. In this drawing the bits within the boxes to the left of the arrows are the only thing that determine whether or not the bit in the box to the right of the arrow can be written. Read access control is not shown in this diagram. Addresses listed in this diagram are for the serial port assuming that the R/W bit in the command byte is set to `0'. For example, when SB1 is a 1, the PB1 field can be written to any value by the system. When the PB1 field is 11, Block 1 can be written to by the system. Note that the state of the SB1 bit does not affect whether or not Block 1 can be written. There is no individual page Write Protection for any other block other than block 0 within the device. Within the remaining blocks on the chip, access permissions are controlled on a block basis (BP bits) or full chip basis (WP pin) only.
Accessed within the Access Protection Page is an individual CMOS Sticky Bit (SB) for each of the 8 blocks on the device. When the value of the sticky bit is `0', the Protection Bits (PB) for the corresponding block may not be changed via the software. These bits are all set to one when power is initially applied or when the PROT pin is LOW. These sticky bits may be written only to a `0' via the serial interface using the standard serial write operations. Reading the sticky bits does not affect their state. Because permissions are set individually for each of the blocks, all reads via serial port will only read bytes within the block that was specified when the current address was latched in the device (with a write command). The block address bits (B2 or B1) that are sent with the write command are ignored on a read command. When a sticky bit is cleared (programmed at 0), the byte containing the sticky bit cannot be changed anymore. If a write operation to this byte is attempted, it will be normally acknowledged but no change
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Philips Semiconductors
Product data
1024 x 8-bit CMOS EEPROM with access protection
PCA24S08
WRITE PROTECTION FLOW
WP A800 SB0 PB0 Page 0 16 bytes A80F A810 SBAP PBAP WPN0 WPN1 Page 1 16 bytes A81F BLOCK 0
A870 WPN7 Page 7 16 bytes
A87F A880
SB1
PB1
Block 1 128 bytes A88FF
AE80 SB7 PB7 Block 7 128 bytes AEFF
SB0
SB0 SB1 SB1
PB0 PB1
B800 B801
SB7
SB7 SBAP
PB7 PBAP
B807 B808 B809
ACCESS PROTECTION PAGE
7 bytes SBAP PBAP ID Page 16 bytes B81F B80F B810
SW02225
Figure 9. Write protection example
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Philips Semiconductors
Product data
1024 x 8-bit CMOS EEPROM with access protection
PCA24S08
ACCESS PROTECTION PAGE
The serial port may be used to read and write the Access Protection Page (APP) and ID Page using device access codes B8h and B9h instead of the normal value of A8h through AFh (hex) that are used to access the rest of the EEPROM memory. The second byte of write commands (the word address) should be in the range of 00h through 0Fh for the APP page and 10h through 1Fh for the ID page. This coding is shown in the Access Protection Page Examples section. Reads and writes to these two pages may take place on a single byte basis only. Multi-byte operations will be NACK'ed. As an example, the bit encoding for a single byte read and write command are shown in the Access Protection Page Examples section. The PCA24S08 will acknowledge all device addresses of B8h or B9h. If the most significant three its of the word address are not all 0 (indicating an address outside the Access protection and ID pages), the chip will NACK the access. Bytes 0 through 7 of the APP contain 8 identical set of access control fields (PBx and SBx) for each of the eight blocks of memory on the chip, which operate according to the table listed in the Access Protection section above. When the sticky bit in one of these bytes is set, that byte can be written by the system. Once a sticky bit is reset (written to zero) by the software, the byte containing it can no longer be modified by the software until the next power cycle. These bytes can always be read by the system. Byte 8 contains another PB field (PBAP) as bits 0 and 1 and an additional sticky bit (SBAP) as bit 7. The value of the PBAP bits controls read and write access to the last 7 bytes (9-15) of the APP and all 16 bytes of the ID page according to the encoding listed in the "Access Protection" section above. The value of the PBAP bits can only be changed, a write from the serial port, when SBAP is HIGH. This byte can always be read by the system. Bit 0 through 6 of this byte are stored in EEPROM memory and do not change when the power is cycled or the PROT pin changes state. Byte 9 contains the 8 block 0 write protection bits (WPN) for each page within block 0. Byte 10 emulates a coil detection feature to keep compatibility with existing software controlling device. Even though the PCA24S08 does not have the RFID capability of the AT24RF03C, it gives a "coil non detected" information when the detection feature is initiated. The detection feature uses the Detection Enable bit (DE) and the Detect Coil bit (DC). At power-up, DE = 0 and DC = 1. Detection is
enabled by setting DE bit at 1. Since no coil is detected, DC is then automatically reset and equal to 0. DE is a Read/Write bit, DC is a Read Only bit. Attempt to write to this bit will be ignored. Bit 0 in the same byte emulates a Tamper bit and is always equal to 0. TAMPER is a Read Only bit. Attempt to write a `1' to this bit will be ignored. Bytes 11 through 14 are currently reserved and should not be used by the system. Byte 14 may not be written by the device at any time. Byte 11 to 13 are read/write bytes that are stored in the EEPROM. Byte 14 is a read only byte and the returned value during a read operation is FFh. A write on it is acknowledged but the write will be ignored.
Device Access Examples
For Write Operations: 1 0 1 1 1 0 0 0 0 0 0 Po A3 A2 A1 A0 D 7 D6 D5 D4 D3 D2 D1 D 0
P0: used to distinguish between the APP and RFID pages P0 = 0: APP pages P0 = 1: RFID pages For Read Operations: 1 0 1 1 1 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 Byte 15 contains device revision information stored in the EEPROM. It is set at the wafer production facility and cannot be changed in the field, so any write to this byte will be ignored but acknowledged. The value of this byte is 10h. The memory map for the access protection page is shown in the APP Memory Map table. In this table, an X means that the value is a don't care upon writing and that it is undefined upon reading. The PB fields are all two bits wide, and the Device Revision field is 8 bits wide. All other fields are on bit wide. With the exception of the 9 sticky bits (SB) the two coil detect bits (DE and DC), the tamper bit (TAMPER) and bytes 14 and 15, all bits within the Access Protection Page are stored in EEPROM memory. Their state does not change if power is removed or when the PROT pin is held LOW. The following page of memory (accessed with A4 = 1) emulate the ID field that would be transmitted by the device from the RFID port. Bytes within it are accessed with the address byte at B8h or B9h (write/read). Reading and writing to this page is permitted when PBAP is 11.
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Philips Semiconductors
Product data
1024 x 8-bit CMOS EEPROM with access protection
PCA24S08
APP MEMORY MAP
ADDRESS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BIT 7 SB0 SB1 SB2 SB3 SB4 SB5 SB6 SB7 SBAP WPN7 DE BIT 6 X X X X X X X X X WPN6 DC X WPN5 X BIT 5 RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 X WPN4 X BIT 4 BIT 3 X X X X X X X X X WPN3 X BIT 2 X X X X X X X X X WPN2 X WPN1 X BIT 1 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PBAP WPN0 TAMPER BIT 0
Reserved R/W Reserved R/W Reserved R/W Reserved R only Device Revision
PROT PIN
The PROT pin is used as a power good signal. When this pin is held LOW, the serial port is held in reset and all sticky bits are set to one. When HIGH, activity on the serial bus is permitted and sticky bits can be set to their values.
* * * * *
The two block address bits (B2 and B1) in the command byte are ignored with all read commands. they are set only via the write command. Multi-byte reads do not cross block boundaries, but instead wrap to the beginning of the block. The serial port will be reset whenever the PROT pin is LOW. If more than 16 bytes are written to the EEPROM with a page write, overlapping bytes will have their values corrupted. If VDD is 0 V, the device draws current on the SDA, SCL, WP, and PROT pins when they are brought above 0 V.
SERIAL EEPROM EXCEPTIONS
In general, the two-wire serial interface on the PCA24S08 functions identically to the 24C08. The following exceptions exist, as noted elsewhere in this document.
* *
Pins 1, 2, and 3 have different usage. Access to various blocks may be restricted via the access protection circuitry.
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Philips Semiconductors
Product data
1024 x 8-bit CMOS EEPROM with access protection
PCA24S08
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. SYMBOL PARAMETER voltage on VDD with respect to ground voltage on SDA, SCL, PROT, and WP Tstg Tamb storage temperature operating temperature MIN -- -0.1 to VDD -55 -40 MAX 4.6 +0.3 +125 +85 UNIT V V _C _C
DC ELECTRICAL CHARACTERISTICS
VDD = 2.5 V to 3.6 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. SYMBOL VDD IDDR IDDW Istb ILIO ILWP VIL VIH VOL CI CIO PARAMETER supply voltage supply current, EEPROM reads supply current, EEPROM writes standby current input/output current, PROT, SDA, SCL input current on WP LOW-level input voltage HIGH-level input voltage LOW-level output voltage input capacitance input/output capacitance IOL = 2.1 mA SCL, PROT, WP not tested SDA not tested VDD = 3.6 V; fSDA = 100 kHz VDD = 3.6 V; fSDA = 100 kHz VDD = 3.6 V; SDA, SCL = VSS VIN = VDD or VSS VWP = VDD = 5.5 V CONDITIONS MIN 2.5 -- -- -- -- -- -0.1 VDD x 0.7 -- -- -- TYP -- 50 0.325 11.4 0.25 -- -- -- -- -- -- MAX 3.6 100 1.0 15 3.0 20 VDD x 0.3 VDD 0.4 6 8 UNIT V A mA A A A V V V pF pF
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Philips Semiconductors
Product data
1024 x 8-bit CMOS EEPROM with access protection
PCA24S08
AC SPECIFICATIONS
CL = 1 TTL gate and 100 pF, except as noted. VDD = 2.5 V to 3.6 V. SYMBOL fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT (L) tVD;DAT (H) tSU;DAT tLOW tHIGH tF tR tSP Operating frequency Bus free time between STOP and START conditions Hold time after (repeated) START condition Repeated START condition setup time Setup time for STOP condition Data in hold time Valid time for ACK condition2 Data out valid time3 Data out valid time3 Data setup time Clock LOW period Clock HIGH period Clock/Data fall time Clock/Data rise time Pulse width of spikes that must be suppressed by the input filters PARAMETER STANDARD MODE I2C-bus MIN 0 4.7 4.0 4.7 4.0 0 -- -- -- 250 4.7 4.0 -- -- -- MAX 100 -- -- -- -- -- 600 600 1500 -- -- -- 300 1000 50 FAST MODE I2C-bus MIN 0 1.3 0.6 0.6 0.6 0 -- -- -- 100 1.3 0.6 20 + 0.1 Cb1 20 + 0.1 Cb --
1
UNITS kHz s s s s ns ns ns ns ns s s ns ns ns
MAX 400 -- -- -- -- -- 600 600 600 -- -- -- 300 300 50
NOTES: 1. Cb = total capacitance of one bus line in pF. 2. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. 3. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
EEPROM MEMORY
NAME Retention Endurance PARAMETER Data retention at operating temperature Per byte MIN 10 100,000 TYP -- -- MAX -- -- UNIT Years Cycles
SDA
tBUF
tLOW
tR
tF
tHD;STA
tSP
SCL
tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr
tSU;STA
tSU;STO P
SU00645
Figure 10. Timing diagram for serial interface AC specifications
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Philips Semiconductors
Product data
1024 x 8-bit CMOS EEPROM with access protection
PCA24S08
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
2004 May 10
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Philips Semiconductors
Product data
1024 x 8-bit CMOS EEPROM with access protection
PCA24S08
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
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Philips Semiconductors
Product data
1024 x 8-bit CMOS EEPROM with access protection
PCA24S08
REVISION HISTORY
Rev _1 Date 20040510 Description Product data (9397 750 13015)
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Philips Semiconductors
Product data
1024 x 8-bit CMOS EEPROM with access protection
PCA24S08
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Level
I
Data sheet status [1]
Objective data
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Date of release: 05-04
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 13015
Philips Semiconductors
2004 May 10 16

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